View HM5117805BSERIES_315014.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

HM5117805B Series
2,097,152-word x 8-bit Dynamic Random Access Memory
ADE-203-457B (Z) Rev. 2.0 Jun. 28, 1996 Description
The Hitachi HM5117805B is a CMOS dynamic RAM organized 2,097,152-word x 8-bit. It employs the most advanced CMOS technology for high performance and low power. The HM5117805B offers Extended Data Out (EDO) Page Mode as a high speed access mode. Multiplexed address input permits the HM5117805B to be packaged in standard 28-pin plastic SOJ and 28-pin TSOP.
Features
* Single 5 V (10%) * High speed Access time: 60 ns/70 ns/80 ns (max) * Low power dissipation Active mode: 660mW/605 mW/550 mW(max) Standby mode : 11 mW (max) : 0.83 mW (max) (L-version) * EDO page mode capability * Long refresh period 2048 refresh cycles : 32 ms : 128 ms (L-version) * 4 variations of refresh RAS-only refresh CAS-before-RAS refresh Hidden refresh Self refresh (L-version) * Battery backup operation (L-version)
This specification is fully compatible with the 16-Mbit DRAM specifications from TEXAS INSTRUMENTS.
HM5117805B Series
Ordering Information
Type No. HM5117805BJ-6 HM5117805BJ-7 HM5117805BJ-8 HM5117805BLJ-6 HM5117805BLJ-7 HM5117805BLJ-8 HM5117805BS-6* 1 HM5117805BS-7* 1 HM5117805BS-8* 1 HM5117805BLS-6* 1 HM5117805BLS-7* 1 HM5117805BLS-8* 1 HM5117805BTT-6 HM5117805BTT-7 HM5117805BTT-8 HM5117805BLTT-6 HM5117805BLTT-7 HM5117805BLTT-8 HM5117805BTS-6*1 HM5117805BTS-7*1 HM5117805BTS-8*1 HM5117805BLTS-6*1 HM5117805BLTS-7*1 HM5117805BLTS-8*1 Note: 1. Under development Access time 60 ns 70 ns 80 ns 60 ns 70 ns 80 ns 60 ns 70 ns 80 ns 60 ns 70 ns 80 ns 60 ns 70 ns 80 ns 60 ns 70 ns 80 ns 60 ns 70 ns 80 ns 60 ns 70 ns 80 ns 300-mil 28-pin plastic TSOP II (TTP-28DB) 400-mil 28-pin plastic TSOP II (TTP-28DA) 300-mil 28-pin plastic SOJ (CP-28DNA) Package 400-mil 28-pin plastic SOJ (CP-28DA)
2
HM5117805B Series
Pin Arrangement
HM5117805BJ/BLJ Series HM5117805BS/BLS Series
VCC I/O0 I/O1 I/O2 I/O3 WE RAS NC A10 A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VSS I/O7 I/O6 I/O5 I/O4 CAS OE A9 A8 A7 A6 A5 A4 VSS
HM5117805BTT/BLTT Series HM5117805BTS/BLTS Series VCC I/O0 I/O1 I/O2 I/O3 WE RAS NC A10 A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 (Top view) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VSS I/O7 I/O6 I/O5 I/O4 CAS OE A9 A8 A7 A6 A5 A4 VSS
(Top view)
Pin Description
Pin name A0 to A10 Function Address input Row/Refresh address A0 to A10 Column address I/O0 to I/O7 RAS CAS WE OE VCC VSS NC Data input/data output Row address strobe Column address strobe Read/Write enable Output enable Power supply Ground No connection A0 to A9
3
HM5117805B Series
Block Diagram
RAS RAS control circuit CAS CAS control circuit WE WE control circuit OE OE control circuit
I/O7
I/O7 buffer
I/O6
I/O6 buffer
Sense amp. & I/O bus
circuit
Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array
Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus
I/O5 buffer
I/O5
Row decoder & driver
Row decoder & driver
I/O4 buffer
I/O4
Column decoder & driver
Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus
Peripheral
Column decoder & driver
Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus 256k memory cell array Sense amp. & I/O bus
Row decoder & driver
I/O3
I/O3 buffer
Row decoder & driver
I/O1 buffer
I/O1
I/O2
I/O2 buffer
I/O0 buffer
I/O0
Column address buffer
Row address buffer
A0 to A9
A0 to A10
4
HM5117805B Series
Absolute Maximum Ratings
Parameter Voltage on any pin relative to V SS Supply voltage relative to VSS Short circuit output current Power dissipation Operating temperature Storage temperature Symbol VT VCC Iout PT Topr Tstg Value -1.0 to +7.0 -1.0 to +7.0 50 1.0 0 to +70 -55 to +125 Unit V V mA W C C
Recommended DC Operating Conditions (Ta = 0 to +70C)
Parameter Supply voltage Input high voltage Input low voltage Note: 1. All voltage referred to V SS . Symbol VCC VIH VIL Min 4.5 2.4 -1.0 Typ 5.0 -- -- Max 5.5 6.5 0.8 Unit V V V Note 1 1 1
5
HM5117805B Series
DC Characteristics (Ta = 0 to +70C, VCC = 5 V 10%, VSS = 0 V)
HM5117805B -6 Parameter Operating current Standby current
*1, *2
-7
-8
Symbol Min Max Min Max Min Max Unit Test conditions I CC1 I CC2 -- -- 120 -- 2 -- 110 -- 2 -- 100 mA 2 mA t RC = min TTL interface RAS, CAS = VIH Dout = High-Z CMOS interface RAS, CAS VCC - 0.2V Dout = High-Z CMOS interface RAS, CAS VCC - 0.2V Dout = High-Z t RC = min RAS = VIH CAS = VIL Dout = enable t RC = min t HPC = min CMOS interface Dout = High-Z CBR refresh: tRC = 62.5 s t RAS 0.3 s CMOS interface RAS, CAS 0.2V Dout = High-Z 0 V Vin 7 V 0 V Vout 7 V Dout = disable High Iout = -2 mA Low Iout = 2 mA
--
1
--
1
--
1
mA
Standby current (L-version)
I CC2
--
150 --
150 --
150 A
RAS-only refresh current*2 Standby current
*1
I CC3 I CC5
-- --
120 -- 5 --
110 -- 5 --
100 mA 5 mA
CAS-before-RAS refresh current EDO page mode current
*4 *1, *3
I CC6 I CC7 I CC10
-- -- --
120 -- 120 -- 500 --
110 -- 110 -- 500 --
100 mA 100 mA 500 A
Battery backup current (Standby with CBR refresh) (L-version) Self refresh mode current (L-version) Input leakage current Output leakage current Output high voltage Output low voltage
I CC11
--
300 --
300 --
300 A
I LI I LO VOH VOL
-10 10 -10 10 2.4 0 VCC 0.4
-10 10 -10 10 2.4 0
-10 10 -10 10 VCC 0.4
A A V V
VCC 2.4 0.4 0
Notes: 1. I CC depends on output load condition when the device is selected. ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less while CAS = VIH. 4. CAS = L ( 0.2 V) while RAS = L ( 0.2 V).
6
HM5117805B Series
Capacitance (Ta = 25C, VCC = 5 V 10%)
Parameter Input capacitance (Address) Input capacitance (Clocks) Output capacitance (Data-in, Data-out) Symbol CI1 CI2 CI/O Typ -- -- -- Max 5 7 7 Unit pF pF pF Notes 1 1 1, 2
Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CAS = VIH to disable Dout.
AC Characteristics (Ta = 0 to +70C, VCC = 5 V 10%, VSS = 0 V)*1, *2, *18
Test Conditions * * * * * Input rise and fall time: 2 ns Input levels: VIL = 0 V, V IH = 3 V Input timing reference levels: 0.8 V, 2.4 V Output timing reference levels: 0.8 V, 2.0 V Output load: 1 TTL gate + C L (100 pF) (Including scope and jig)
7
HM5117805B Series
Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters)
HM5117805B -6 Parameter Random read or write cycle time RAS precharge time CAS precharge time RAS pulse width CAS pulse width Row address setup time Row address hold time Column address setup time Column address hold time RAS to CAS delay time RAS to column address delay time RAS hold time CAS hold time CAS to RAS precharge time OE to Din delay time OE delay time from Din CAS delay time from Din Transition time (rise and fall) Symbol Min t RC t RP t CP t RAS t CAS t ASR t RAH t ASC t CAH t RCD t RAD t RSH t CSH t CRP t OED t DZO t DZC tT 104 40 10 60 10 0 10 0 10 20 15 15 48 5 15 0 0 2 Max -- -- -- -7 Min 124 50 13 Max -- -- -- -8 Min 144 60 15 Max -- -- -- Unit Notes ns ns ns
10000 70 10000 13 -- -- -- -- 45 30 -- -- -- -- -- -- 50 0 10 0 13 20 15 18 58 5 18 0 0 2
10000 80 10000 15 -- -- -- -- 52 35 -- -- -- -- -- -- 50 0 10 0 15 20 15 20 68 5 20 0 0 2
10000 ns 10000 ns -- -- -- -- 60 40 -- -- -- -- -- -- 50 ns ns ns ns ns ns ns ns ns ns ns ns ns 5 6 6 7 3 4
8
HM5117805B Series
Read Cycle
HM5117805B -6 Parameter Access time from RAS Access time from CAS Access time from address Access time from OE Read command setup time Read command hold time to CAS Read command hold time from RAS Read command hold time to RAS Column address to RAS lead time Column address to CAS lead time CAS to output in low-Z Output data hold time Output data hold time from OE Output buffer turn-off time Output buffer turn-off to OE CAS to Din delay time Output data hold time from RAS Output buffer turn-off to RAS Output buffer turn-off to WE WE to Din delay time RAS to Din delay time Symbol Min t RAC t CAC t AA t OEA t RCS t RCH t RCHR t RRH t RAL t CAL t CLZ t OH t OHO t OFF t OEZ t CDD t OHR t OFR t WEZ t WED t RDD -- -- -- -- 0 0 60 0 30 18 0 3 3 -- -- 15 3 -- -- 15 15 Max 60 15 30 15 -- -- -- -- -- -- -- -- -- 15 15 -- -- 15 15 -- -- -7 Min -- -- -- -- 0 0 70 0 35 23 0 3 3 -- -- 18 3 -- -- 18 18 Max 70 18 35 18 -- -- -- -- -- -- -- -- -- 15 15 -- -- 15 15 -- -- -8 Min -- -- -- -- 0 0 80 0 40 28 0 3 3 -- -- 20 3 -- -- 20 20 Max 80 20 40 20 -- -- -- -- -- -- -- -- -- 15 15 -- -- 15 15 -- -- Unit Notes ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 13, 20 13 5 20 20 20 12 12 8, 9 9, 10, 17 9, 11, 17 9
9
HM5117805B Series
Write Cycle
HM5117805B -6 Parameter Write command setup time Write command hold time Write command pulse width Write command to RAS lead time Write command to CAS lead time Data-in setup time Data-in hold time Symbol Min t WCS t WCH t WP t RWL t CWL t DS t DH 0 10 10 10 10 0 10 Max -- -- -- -- -- -- -- -7 Min 0 13 10 13 13 0 13 Max -- -- -- -- -- -- -- -8 Min 0 15 10 15 15 0 15 Max -- -- -- -- -- -- -- Unit Notes ns ns ns ns ns ns ns 15 15 14
Read-Modify-Write Cycle
HM5117805B -6 Parameter Read-modify-write cycle time RAS to WE delay time CAS to WE delay time Column address to WE delay time OE hold time from WE Symbol Min t RWC t RWD t CWD t AWD t OEH 149 82 37 52 15 Max -- -- -- -- -- -7 Min 175 95 43 60 18 Max -- -- -- -- -- -8 Min 199 107 47 67 20 Max -- -- -- -- -- Unit Notes ns ns ns ns ns 14 14 14
Refresh Cycle
HM5117805B -6 Parameter CAS setup time (CBR refresh cycle) CAS hold time (CBR refresh cycle) WE setup time (CBR refresh cycle) WE hold time (CBR refresh cycle) RAS precharge to CAS hold time Symbol Min t CSR t CHR t WRP t WRH t RPC 5 10 0 10 0 Max -- -- -- -- -- -7 Min 5 10 0 10 0 Max -- -- -- -- -- -8 Min 5 10 0 10 0 Max -- -- -- -- -- Unit Notes ns ns ns ns ns
10
HM5117805B Series
EDO Page Mode Cycle
HM5117805B -6 Parameter EDO page mode cycle time EDO page mode RAS pulse width Access time from CAS precharge Symbol Min t HPC t RASP t CPA 25 -- -- 35 3 10 5 35 Max -- -7 Min 30 Max -- -8 Min 35 Max -- Unit Notes ns 19 16 9, 17
100000 -- 35 -- -- -- -- -- -- 40 3 13 5 40
100000 -- 40 -- -- -- -- -- -- 45 3 15 5 45
100000 ns 45 -- -- -- -- -- ns ns ns ns ns ns
RAS hold time from CAS precharge t CPRH Output data hold time from CAS low t DOH CAS hold time referred OE CAS to OE setup time t COL t COP
9, 17
Read command hold time from CAS t RCHC precharge
EDO Page Mode Read-Modify-Write Cycle
HM5117805B -6 Parameter EDO page mode read- modify-write cycle time WE delay time from CAS precharge Symbol Min t HPRWC t CPW 79 54 Max -- -- -7 Min 90 62 Max -- -- -8 Min 99 69 Max -- -- Unit Notes ns ns 14
Refresh
Parameter Refresh period Refresh period (L-version) Symbol t REF t REF Max 32 128 Unit ms ms Note 2048 cycles 2048 cycles
11
HM5117805B Series
Self Refresh Mode (L-version)
HM5117805BL -6 Parameter RAS pulse width (self refresh) RAS precharge time (self refresh) CAS hold time (self refresh) Symbol Min t RASS t RPS t CHS 100 110 -50 Max -- -- -- -7 Min 100 130 -50 Max -- -- -- -8 Min 100 150 -50 Max -- -- -- Unit Notes s ns ns
Notes: 1. AC measurements assume t T = 2 ns. 2. An initial pause of 200 s is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing RAS-only refresh or CAS-before-RAS refresh). If the internal refresh counter is used, a minimum of eight CAS-before-RAS refresh cycles are required. 3. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only; if t RCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC . 4. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only; if t RAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA . 5. Either t OED or tCDD must be satisfied. 6. Either t DZO or tDZC must be satisfied. 7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between V IH (min) and VIL (max). 8. Assumes that t RCD tRCD (max) and tRAD tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, t RAC exceeds the value shown. 9. Measured with a load circuit equivalent to 1 TTL loads and 100 pF. 10. Assumes that t RCD tRCD (max) and tRAD tRAD (max). 11. Assumes that t RCD tRCD (max) and tRAD tRAD (max). 12. Either t RCH or tRRH must be satisfied for a read cycles. 13. t OFF (max) and tOEZ (max) define the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. 14. t WCS , t RWD, t CWD, t AWD and t CPW are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only; if t WCS tWCS (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if t RWD tRWD (min), tCWD tCWD (min), and tAWD tAWD (min), or tCWD tCWD (min), tAWD tAWD (min) and tCPW tCPW (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 15. These parameters are referred to CAS leading edge in early write cycles and to WE leading edge in delayed write or read-modify-write cycles. 16. t RASP defines RAS pulse width in EDO page mode cycles. 17. Access time is determined by the longest among t AA , t CAC and t CPA. 18. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device.
12
HM5117805B Series
19. t HPC (min) can be achieved during a series of EDO page mode write cycles or EDO page mode read cycles. If both write and read operation are mixed in a EDO page mode RAS cycle (EDO page mode mix cycle (1), (2)), minimum value of CAS cycle (tCAS + tCP + 2 tT) becomes greater than the specified t HPC (min) value.The value of CAS cycle time of mixed EDO page mode is shown in EDO page mode mix cycle (1) and (2). 20. Data output turns off and becomes high impedance from later rising edge of RAS and CAS. Hold time and turn off time are specified by the timing specifications of later rising edge of RAS and CAS between tOHR and t OH, and between tOFR and t OFF. 21. Please do not use tRASS timing, 10 s tRASS 100 s. During this period, the device is in transition state from normal operation mode to self refresh mode. If t RASS 100 s, then RAS precharge time should use t RPS instaed of tRP. 22. If you use RAS only refresh or CBR burst refresh mode in normal read/write cycles, 2048 cycles of distributed CBR refresh with 15.6 Ms interval should be executed within 32 ms immediately after exiting from and before entering into the self refresh mode. 23. If you use distributed CBR refresh mode with 15.6 s interval in normal read/write cycle, CBR refresh should be executed within 15.6 s immediately after exiting from and before entering into self refresh mode. 24. Repetitive self refresh mode without refreshing all memory is not allowed. Once you exit from self refresh mode, all memory cells need to be refreshed before re-entering the self refresh mode again. 25. XXX: H or L (H: V IH (min) VIN VIH (max), L: VIL (min) VIN VIL (max)) ///////: Invalid Dout When the address, clock and input pins are not described on timing waveforms, their pins must be applied V IH or VIL.
13
HM5117805B Series
Timing Waveforms*25
Read Cycle
t RC t RAS t RP
RAS t CSH t RCD tT t RSH t CAS t CRP
CAS
t RAD t ASR t ASC t RAL t CAL t CAH
t RAH
Address
Row
Column t RRH t RCHR t RCS t RCH
WE t WED t DZC t CDD t RDD Din High-Z
t DZO
t OEA
t OED
OE t OEZ t OHO t OFF t OH t OFR t OHR t WEZ Dout Dout
t CAC t AA t RAC t CLZ
14
HM5117805B Series
Early Write Cycle
t RC t RAS t RP
RAS t CSH t RCD tT CAS t RSH t CAS t CRP
t ASR
t RAH
t ASC
t CAH
Address
Row
Column
t WCS
t WCH
WE
t DS
t DH
Din
Din
Dout
High-Z* * t WCS t WCS (min)
15
HM5117805B Series
Delayed Write Cycle*18
t RC t RAS
t RP
RAS t CSH t RCD tT CAS t ASR t RAH t ASC t CAH t RSH t CAS t CRP
Address
Row
Column t CWL t RCS t RWL t WP
WE
t DZC
t DS
t DH
Din
High-Z
Din t OEH t OED
t DZO

OE t OEZ t CLZ Dout High-Z Invalid Dout 16
HM5117805B Series
Read-Modify-Write Cycle*18
t RWC t RAS
t RP
RAS tT t RCD t CAS t CRP
CAS t RAD t ASR t RAH t ASC t CAH
Address
Row t RCS
Column t CWD t AWD t RWD tCWL t RWL t WP
WE t DZC t DS Din
High-Z Din
t DH
t DZO
t OED t OEA
t OEH
OE t CAC t AA t RAC t OEZ t OHO
High-Z
Dout t CLZ
Dout
17
HM5117805B Series
RAS-Only Refresh Cycle
t RC t RAS RAS tT t CRP CAS t RPC t CRP t RP
t ASR Address t OFR t OFF Dout Row
t RAH
High-Z
18
HM5117805B Series
CAS-Before-RAS Refresh Cycle
t RC t RP RAS t RPC CAS t CSR tT t CHR t RPC t CRP t RAS t RP
,
t CP t WRP t WRH t CP WE Address t OFR t OFF Dout High-Z 19
HM5117805B Series
Hidden Refresh Cycle
t RC t RAS t RC t RAS t RC t RP t RAS t RP
t RP
RAS tT t RSH t RCD
CAS
t CHR
t CRP
t RAD t ASR t RAH Address Row t ASC
t RAL t CAH
Column t RRH t RCH

WE t DZC High-Z Din t DZO t OEA OE t CAC t AA t RAC t CLZ Dout Dout
t RCS
t RRH
t WRH t WRP
t WRP
tWRH
t WED t CDD t RDD
t OED
t OFF t OH
t OEZ t WEZ t OHO
t OFR t OHR
20
HM5117805B Series
EDO Page Mode Read Cycle
t RP
RAS
t RASP tT t CSH t CAS t RCS t RCHR t RCH t RCS t CP t HPC t CAS t CP t HPC tCAS t RCHC
t HPC t CPRH t CP t t CRP
RSH
CAS
tCAS t RRH t RCH
WE
tASR
Address
tRAH tASC Row
tCAH
t ASC t CAH Column 2 t CAL
t ASC t CAH Column 3 t CAL
tASC
t RAL t CAH
Column 4
t WED
Column 1 t CAL tDZC
t CAL tRDD tCDD
Din
High-Z tDZO tCOL tCOP tOED

OE
tOEA
tCPA
tCPA
tCAC tAA
tAA tCAC
tOEZ
tWEZ
tOHO
tCPA tAA tCAC
tAA
tOEZ
tOFR tOHR tOEZ
tCAC
tRAC
tOEA
tDOH
tOHO
tOEA
tOHO tOFF tOH
Dout
Dout 1
Dout 2
Dout 2
Dout 3
Dout 4
21
HM5117805B Series
EDO Page Mode Early Write Cycle
t RASP
t RP
RAS tT t CSH t RCD t CAS CAS t CP t HPC t CAS t CP t RSH t CAS t CRP
t ASR t RAH
t ASC
t CAH
t ASC
tCAH
t ASC t CAH
Address
Row
Column 1
Column 2
Column N
t WCS
t WCH
t WCS
t WCH
t WCS
t WCH
WE
t DS
t DH
t DS
t DH
t DS
t DH
Din
Din 1
Din 2
Din N
Dout
High-Z* * t WCS t WCS (min)
22
HM5117805B Series
EDO Page Mode Delayed Write Cycle*18
t RASP t RP RAS tT t CSH t RCD
CAS
t CP t CAS t HPC t CAS
t CP t RSH t CAS
t CRP
t RAD t ASR t RAH Address Row t ASC t CAH Column 1 t CWL t RCS WE t WP t DZC t DS t DH Din t DZO t OED Din 1 t DZO t OED t WP t DZC t DS t DH Din 2 t DZO t OED t WP t DZC t DS t DH Din N t RCS t ASC t CAH Column 2 t CWL t RCS t ASC t CAH Column N t CWL t RWL

t OEH t OEH t OEH OE t CLZ t CLZ t CLZ t OEZ t OEZ t OEZ Dout High-Z
Invalid Dout Invalid Dout Invalid Dout
23
HM5117805B Series
EDO Page Mode Read-Modify-Write Cycle*18
t RASP t RP RAS tT t CP t RCD
CAS
t HPRWC t CP t CAS t CAS
t RSH t CAS
t CRP
t RAD t ASR t ASC t RAH Row t CAH Column 1 t RWD t AWD t CWD WE t RCS t WP t DZC t DS t DH Din t DZO
t OED
t ASC t CAH Column 2 t CWL t RCS t CPW t AWD t CWD t RCS t CWL
t ASC t CAH Column N t CPW t AWD t CWD t RWL t CWL
Address
t WP t DZC t DS t DH Din 2 t OED t OEH t DZO t OED
t WP t DZC t DS t DH Din N
Din 1 t DZO t OEH
t OEH
*
OE t OHO t OHO t OHO t AA t OEA t CAC t RAC t AA t CPA t OEA t CAC t AA t CPA t OEA t CAC t CLZ t OEZ t CLZ t OEZ t CLZ t OEZ
High-Z
Dout
Dout 1
Dout 2
Dout N
24
HM5117805B Series
EDO Page Mode Mix Cycle (1)
t RP
RAS
t RASP t CRP tCAS tRSH t RCS tCPW tAWD t ASC tRAH Row tCAH t ASC t CAH Column 2 t CAL tASC t CAH Column 3 t CAL t DS High-Z tOED t DH Din 3 tWED tWP t RAL t CAH Column 4 t CAL tRDD tCDD t RCS t RRH t RCH
tT
CAS
t CP t CAS t CSH t RCD t WCS t WCH t CAS
t CP tCAS
t CP
WE
tASR
Address
tASC
Column 1 t CAL
t DS
Din
t DH Din 1

OE
tCPA tAA tOEA
tCPA
tCPA tAA
t OEZ
tAA
tOFR tWEZ tOEZ
tCAC
tOHO tOFF tOH
tCAC
t DOH
tCAC t OHO
tOEA
Dout
Dout 2
Dout 3
Dout 4
25
HM5117805B Series
EDO Page Mode Mix Cycle (2)
t RP
RAS
t RASP
tT
CAS
t CSH t CAS t RCD t RCS t RCHR
t CP t CAS
t CP tCAS
t CP tCAS t RCS tCPW tWP t RAL tASC t CAH Column 4 t CAL t DS t DH Din 3 tOED tCOP tRSH
t CRP
t RCH tWCS t WCH
t RCS
t RRH t RCH
WE
tASR
Address
tRAH Row
t ASC
tCAH
t ASC t CAH Column 2 t CAL t DS t DH Din 2 tOED
t ASC t CAH Column 3 t CAL
Column 1 t CAL
tRDD tCDD
Din
High-Z
tWED
OE
tCOL t OEA tOEZ t OHO tCPA tAA tCAC tOEZ t OHO
Dout 3
tAA tOEA tCAC tRAC
tCPA tAA tCAC tOEA
tOFR tWEZ tOEZ tOHO tOFF tOH Dout 4
Dout
Dout 1
26
HM5117805B Series
Self Refresh Cycle (L-version)* 21, 22, 23, 24
t RASS
t RP
t RPS
RAS t RPC tT t CRP t CHS
, ,
t CP t CSR CAS t WRP WE t OFR t OFF Dout
t WRH
, + & $
High-Z 27
HM5117805B Series
Package Dimensions
HM5117805BJ/BLJ Series (CP-28DA)
18.17 18.54 Max
Unit: mm
28
15
10.16 0.13
1
3.50 0.26
1.30 Max
0.43 0.10
1.27 0.10
0.80
9.40 0.25
HM5117805BS/BLS Series (CP-28DNA)
2.85 0.12
0.74
14
11.18 0.13
+0.25 -0.17
Unit: mm
18.41 18.84 Max
28
15
7.62 0.12
1
3.50 0.26
1.165 Max
0.43 0.10
1.27 0.10
0.64 Min
6.79 0.18
28
2.45 0.12
0.74
14
8.51 0.12
HM5117805B Series
Package Dimensions (cont)
HM5117805BTT/BLTT Series (TTP-28DA)
Unit: mm
18.41 18.81 Max 28 15
1 0.40 0.10
1.27 0.21 M
14
10.16
11.76 0.2 0 - 5
1.20 Max
0.10 1.15 Max
0.145
0.08 Min 0.18 Max
+0.075 -0.025
0.68 0.50 0.10
HM5117805BTS/BLTS Series (TTP-28DB)
Unit: mm
18.41 18.81 Max 28 15
1 0.40 0.10
1.27 0.21 M
14
7.62
9.22 0.2 0 - 5
1.20 Max
0.10 1.15 Max
0.145 -0.025
0.08 Min 0.18 Max
+0.075
0.63 0.50 0.10
29
HM5117805B Series
When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi's permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user's unit according to this document. 4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi's semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. 6. MEDICAL APPLICATIONS: Hitachi's products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi's sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi's products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS.
Hitachi, Ltd.
Semiconductor & IC Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 For further information write to: Hitachi America, Ltd. Semiconductor & IC Div. 2000 Sierra Point Parkway Brisbane, CA. 94005-1835 USA Tel: 415-589-8300 Fax: 415-583-4207
Hitachi Europe GmbH Electronic Components Group Continental Europe Dornacher Strae 3 D-85622 Feldkirchen Munchen Tel: 089-9 91 80-0 Fax: 089-9 29 30 00
Hitachi Europe Ltd. Electronic Components Div. Northern Europe Headquarters Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA United Kingdom Tel: 0628-585000 Fax: 0628-778322
Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 0104 Tel: 535-2100 Fax: 535-1533 Hitachi Asia (Hong Kong) Ltd. Unit 706, North Tower, World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel: 27359218 Fax: 27306071
30
HM5117805B Series
Revision Record
Rev. 0.0 1.0 Date Sep. 8, 1995 Dec. 25, 1995 Contents of Modification Initial issue Deletion of preliminary Timing waveforms Deletion of note: t OEH tCWE Addit ion of H M5117805BTS/ BLTS Series ( TTP-28DB) Addit ion of HM5117805BS/ BLS Series ( 28DNA) CPRecommended DC Operating Conditions V IH max: 6.0 V to 6.5 V DC characteristics ILI test conditions: 0 V Vin 6.0 V to 0 V Vin 7.0 V ILO test conditions: 0 V Vout 6.0 V to 0 V Vout 7.0 V AC characteristics Change of notes18 and 25 Timing waveforms Change of early write cycle and EDO page mode early write cycle Drawn by Approved by Y. Takahashi K. Hayakawa J. Miyake K. Hayakawa
2.0
Jun. 28, 1996
31

▲Up To Search▲

Price & Availability of HM5117805BSERIES

	To Download HM5117805BSERIES Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .